1. Technical Field
The disclosed embodiments relate to the Phase-Locked Loops (PLLs), and more particularly to PLLs usable in local oscillators within radio receivers and transmitters.
2. Background Information
Phase-Locked Loops (PLLs) are used in many applications, including use in the local oscillators of cellular telephone receivers and transmitters. There are different circuits that can be used to realize such a PLL. Possibilities for realizing the PLL of a local oscillator include analog PLLs and so-called “All-Digital” PLLs (ADPLLs). One type of ADPLL is a Time-to-Digital Converter All-Digital Phase-Locked Loop (TDC ADPLL). FIG. 1 (Prior Art) is a diagram of a TDC ADPLL 1. TDC ADPLL 1 includes an accumulator 2, a Time-to-Digital Converter (TDC) 3, a summer 4, a digital loop filter 5, and a Digitally-Controlled Osciallator (DCO) 6. A second type of ADPLL is a Phase-to-Digital Converter All-Digital Phase-Locked Loop (PDC ADPLL). FIG. 2 (Prior Art) is a diagram of a Phase-to-Digital Converter All-Digital Phase-Locked Loop (PDC ADPLL) 7. PDC ADPLL 7 includes a Phase-to-Digital Converter (PDC) 8, a digital loop filter 9, a DCO 10, and a digital loop divider 11. In both ADPLL architectures, a delay line is used to measure timing in the time domain, and to convert a time difference between signal edges into a digital value. The control loop is often sensitive to reference clock jitter, to jitter of multiples of the reference clock, and/or to other noise. The mechanisms by which such sources of noise interfere with proper operation of the ADPLL can be complex. Achieving proper control and calibration of the delay line can be difficult. The design of the timing control circuitry can be complex.
Another possibility for realizing the PLL of a local oscillator is an analog PLL. FIG. 3 (Prior Art) is a diagram of a fractional-N analog PLL 12. Analog PLL 12 includes a phase detector 13, an analog charge pump 14, an analog filter 15, a Voltage-Controlled Oscillator (VCO) 16, and a divider 17. In this example, the analog PLL 12 is a fractional-N PLL, and includes a delta-sigma modulator 18. In a cellular telephone application, such an analog PLL circuit topology is generally simpler to design and to build and to debug than an ADPLL, but it involves an analog charge pump and an analog loop filter. Due to limiting headroom and footroom requirements of an analog charge pump, an ADPLL generally cannot operate at low supply voltages. Moreover, in a cellular telephone application, a single integrated PLL circuit is to be able to operate in multiple different frequency bands. Unlike a digital loop filter whose coefficients can be changed, an analog loop filter is generally less flexible. It is sometimes difficult or impossible to make a single ADPLL circuit operate satisfactorily in the multiple different frequency bands as required in a cellular telephone application. Moreover, an analog loop filter may require a large amount of die space to implement, and therefore may be undesirably expensive and may require the use of off-chip components.